The present invention relates to integrated circuits, and more particularly to nonvolatile memories.
FIG. 1 illustrates an electrically erasable programmable read-only memory array (EEPROM) described in U.S. Pat. No. 6,420,231 issued Jul. 16, 2002 to Harari et al. and incorporated herein by reference. FIG. 2 is a circuit diagram of the array. Each memory cell 110 has two conductive floating gates 120 positioned side by side in the X direction (row direction) over planar top surface 124T of silicon substrate 124. The floating gates are insulated from the substrate. In the Y direction (column direction), the adjacent floating gates are separated by field oxide regions 130. The floating gates are formed from the first polysilicon layer.
Steering gates 134 are formed from the second polysilicon layer and are insulated from the floating gates. Each steering gate extends in the Y direction between two columns of memory cells 110 and overlies two adjacent columns of floating gates 120. Bitlines 138 are diffusion regions in substrate 124. Each bitline 138 runs in the Y direction between two adjacent columns of floating gates 120. In each row, a bitline 138 provides two source/drain regions to respective two adjacent memory cells 110.
Wordlines 144, formed from the third polysilicon layer, overlie the steering gates and extend in the X direction. Wordlines 144 may also be formed from polycide. The wordline layer also provides select gates 144S (FIG. 1) for the memory cells.
Metal strap lines (not shown) reduce the resistance of the polysilicon elements and diffusion elements of the array.
The memory operates as follows. Each cell 110 can be represented as having two floating gate transistors 110L, 110R (FIG. 2) separated by a select gate transistor 110S (a transistor with gate 144S). The floating gate of transistor 110L is selected for reading or programming by placing a sufficient voltage on the steering gate 134 above the floating gate of transistor 110R to turn on the transistor 110R regardless of the charge on its floating gate. Likewise, the floating gate of transistor 10R is selected for reading or programming by placing a sufficient voltage on the steering gate 134 above the floating gate of transistor 10L to turn on the transistor 10L regardless of the charge on its floating gate. Each floating gate can be read by providing a voltage difference between the respective bitlines 138 and sensing the state of one of the bitlines. A negative charge can be written to a floating gate by source side hot electron injection. The floating gates can be erased through wordlines 144 or substrate 124. See U.S. Pat. No. 6,266,278 issued Jul. 24, 2001 to Harari et al. and incorporated herein by reference.
As noted above, floating gates 120 are made from the first polysilicon layer, steering gates 134 are made from the second polysilicon layer, and wordlines 144 are made from the third polysilicon layer or a polycide layer which also provides the select gates 144S. Alternative fabrication techniques are desirable.